Access control system for a multi-channel transmission ring

ABSTRACT

A node for an access control system for a multi-channel data transmission ring is disclosed. Access to a channel is controlled exclusively by one node, which is the only data receiving node connected to that channel. The receiving node generates slots so that other connected nodes can transfer data to the receiving node. The receiving node can provide balanced access to the channel by all connected nodes. Further embodiments feature prevention of congestion in the buffer of the receiving node. The invention is particularly useful for wavelength division multiplexed (WDM) optical rings.

The invention relates to an access control system for a multi-channeldigital data transmission ring, especially for an optical ring withwavelength division multiplexing, in which a user or node is exclusivelyassigned as a data receiving user or node to each of the channels. Inparticular, the invention pertains to a node applicable in the describedaccess control system.

BACKGROUND OF THE INVENTION

The technical field of the invention relates to communication networksfor digital data transmission having a multi-channel ring topology. Thenetworks referred to are known under the abbreviation LAN for Local AreaNetwork, MAN for Metropolitan Area Network, and to a certain extent asWAN for Wide Area Network, respectively.

In a communication network, multiple users or nodes are interconnectedby at least one transmission medium. In a ring topology, allnode-to-node connections form together a circle through which the dataare passed from a transmitting to a receiving node. Rings can berealized using transmission media like twisted pairs of wire, coaxialcables, or optical fibers. Several well known techniques can be employedto establish a multi-channel ring: The simplest approach is to use anumber of parallel cables or fibers to interconnect the users of thering. Another approach utilizes multiplexing techniques. Inmultiplexing, a common physical connection is shared between the usersby dividing, for instance, the available bandwidth of of a transmittingmedium into fractions exclusively accessible by one user, thesefractions being either frequency fractions (frequency divisionmultiplexing or FDM) or fractions of the complete bandwidth (timedivision multiplexing or TDM) referred to as time slots. The fraction ofthe total bandwidth is also referred to as logical channel in contrastto the physical "real" channel. While in electrical signal transmissionthe frequency multiplexing scheme is known as frequency divisionmultiplexing, in optical networks the term wavelength divisionmultiplexing (WDM) is preferred.

A WDM ring is described in the European patent application EP-A 0520494.From this application, a data transmission system is known, wherein eachnode is assigned to a wavelength different from other nodes, so, when itdetects data on said wavelength, it receives said data for dataprocessing, while data on other wavelengths are passed through. When thenode transmits data to one of the other nodes, it generates data havingthe wavelength assigned to this destination node. Thus, every wavelengthhas the meaning of an address of the destination node. Further, to everynode on the ring at least one time slot for each wavelength is assigned.Thus, the data transfer is strictly pre-coordinated or synchronized.While effectively preventing a collision of data transmitted to thechannel, the fixed pre-coordination deteriorates the throughput of thechannel, as transmitting users cannot take advantage of free time slotsassigned to other nodes.

The method used in EP-A-0520494 and other methods allowing participationof multiple users in a network are generally known as medium accesscontrol (MAC) protocols. A MAC protocol serves to control the access ofthe users to the network, to direct the data from the sending or callinguser to the receiving user, to prevent the loss of data, and the like. Amajor task of such a protocol is to guarantee a fair access of all usersor nodes to the connecting network by predetermined criteria. Thesecriteria may include the designation of priorities to certain nodes, thebalance between heavy users of the network and occasional users, andmanaging access loads that exceed the maximum throughput of the network.

An approach (static FDM or TDM) in a MAC is to assign a portion of thetransmission capacity to a certain user. However, static assignment iswell known for its poor performance. Due to that reason, much work hasbeen concentrated on dynamic bandwidth allocation methods. Two mediumaccess schemes have won dominance in the art, one of which is based onrandom access Carrier Sense Multiple Access (CSMA) type protocols whilethe other scheme is characterized by controlled access token-passingtype protocols.

Furthermore, a slotted transmission structure is known, for example,from a reservation based MAC protocol, i.e. the Cyclic ReservationMultiple Access (CRMA) protocol, which supports any combination offrame-oriented LAN and cell-oriented asynchronous transfer mode (ATM)data transmission. A CRMA protocol for bus topologies is described, forexample, by M. M. Nassehi in: Eighth Annual EFOC/LAN Conference, Munich,June 1990, paper 5.3.4, pp. 246-251. In CRMA, one node, i.e. the headendor scheduler, issues continuously slots, identified by a start/enddelimiter pair or by a characteristic header sequence. The transmittingnodes of the network transfer the data cells or frames into said slots,together with two address labels, indicating the source and thedestination of the data. The CRMA protocol includes a reservation basedfairness scheme to prevent that the first nodes of the network areoccupying exclusively the slots.

It is an object of the invention to provide means to control the accessof multiple users or nodes to a slotted transmission medium divided intodifferent channels, wherein each node is assigned to one channel asreceiving node. More specifically, the invention provides means formultiple access control ensuring fairness, data flow, and congestioncontrol. A particular object of the invention is to provide such meansfor an optical ring using wavelength division multiplexing. These andfurther objects of the invention will become apparent from the followingdescription of the invention.

SUMMARY OF THE INVENTION

According to the invention, a node in the described digital datatransmission system comprises first means to transmit data to channelsassigned to other nodes, second means to generate slots in which theother nodes can asynchronously insert the data to be transmitted to saidnode, said slots having at least one bit indicating a busy/free statuswhich is set by the transmitting node, and third fairness control meansto provide a balanced access to said slots to all nodes having data totransmit on said channel in case of the amount of data to be transmittedexceeds the capacity of said channel.

Thus, a node which controls a channel provides the slots into which thetransmitting nodes insert the data designated to said node. As mentionedabove, slots are identified by a start/end delimiter pair or by acharacteristic header sequence. In contrast to the known access schemesfor transmission media divided into channels controlled by differentnodes, which only allow strictly synchronized data transmission inpreassigned slots, as described in EP-A 0520494 the transmitting nodesaccording to the invention are allowed to transmit their data into anypassing unoccupied slot, unless the capacity of the channel is exceeded.The status of a slot is indicated by an appropriate setting of thebusy/free bit. The transmitting node sets the busy/free bit and, hence,prevents that other transmitting nodes try to gain access to theoccupied slot. The asynchronous access exploits the capacity of achannel generally better than the strictly synchronized datatransmission, in which the time slot assigned to one transmitting nodecannot be occupied by another node.

In order to prevent an unbalance in access opportunities between thetransmitting nodes for the generated slots in case that the amount ofdata to be transmitted is exceeding the capacity of the channel, eachchannel controlling node is provided with fairness control means,preferably comprising means to periodical generate a poll slot (reservecommand). The time between two consecutive reserve commands or thenumber of slots generated between the two reserve commands is defined asreservation cycle.

The reserve command serves two purposes: Firstly, it notifies a fairnessthreshold value (TH) for the immediately following reservation cycle tothe nodes which are currently tuned to its channel, i.e. the nodes whichwant to transmit data to the channel controlling destination node.Secondly, the reserve command gathers a value (QL) indicating the amountof data to be transmitted on the considered channel from each of thenodes tuned to that channel. The QL values are used to determine thethreshold value (TH) for the next reserve command. If the demand doesnot exceed the capacity of the channel, the threshold value is set to anumber, e.g. 0, indicating that the nodes are free to access as many ofthe passing unoccupied slots as required. If, however, the summed demandexceeds the capacity of the channel, the slots generated during thefollowing cycle are marked as reserved by setting another bit, i.e. thereserve bit, within each slot. As a transmitting node, each nodecomprises further means to determine the amount of data allowed to betransmitted to another node according to the threshold value (TH)received by the node which controls the channel.

In another preferred embodiment of the invention, a node comprises abuffer, in which the data received from the medium can be stored. Toprevent an overflow of the receiver buffer, flow control means monitorthe extent to which the buffer is filled and throttle the generation offree slots, accordingly. The signal to throttle the free slot generationmight as well be triggered from another circuitry the capacity of whichbeing stressed critically. It is an advantage of the invention that theflow control on the transmission medium is achievable by simply markingpart of the generated slots as busy, thus, preventing an access oftransmitting nodes.

In addition to the flow control or instead of it, a node preferablycomprises congestion control means, which also depends on the grade towhich said buffer means is occupied and is using the channel as anintermediate storage. A possible way to exploit the transmission mediumas an intermediate storage, according to the invention, is to let thechannel controlling node generate a specific slot (congestion command)which causes all nodes to stop transmission on its channel. The incomingoccupied slots are relayed back to the transmission medium. In case ofan optical transmission medium, the slots are either reverted to thering before the opto-electrical conversion by a switch controlledthrough the congestion control or by using the slot generator toreconstruct the received slots after opto-electrical conversion and feedthese slots back to the ring by the same means as applied to freshlygenerated slots.

In many applications, specific priority schemes are required to controlthe access to the transmission medium according to different functionsof the connected nodes, e.g. in real time applications like voice andvideo transmission. For example, in voice transmission, a node demands aguaranteed bandwidth to prevent a distortion or an interruption of thetransmitted speech. To allocate a demand for guaranteed slotsdynamically, i.e. according to the actual need, a node comprisespriority access control means or guaranteed bandwidth control meansperiodically generating a poll slot (priority or guarantee command) tocollect the demand for priority or guaranteed bandwidth slots to betransmitted on its channel node from each of the other nodes tuned tothat channel. According to the number of requested priority orguaranteed slots and the capacity of its channel, the slot generatorproduces slots marked by special bits as priority or guaranteed slots.If both types of slots are requested, the guaranteed slots shouldpreferably be generated before the priority slots. The nodes monitor thepassing slots and occupy the first free priority or guaranteed slotswith their data.

As in periods of high data traffic on a channel, almost every generatedslot will be marked according to the invention as priority slot, asguaranteed, or as reserved, and as there is necessarily a delay of oneround-trip between the reported demand and the generation of therespective slots, a node may have a reduced QL or even no data totransmit at the arrival of the slots demanded through the last polling.To maintain nevertheless a high throughput, the generated slotspreferably have at least another bit (release bit) to cancel the effectof the reservation and free the unoccupied slot for the use by othernodes in case of an all optical transmission medium. The release bit isset by the data transmitting node. In case that the transmission mediumis intermediately converted into the electrical domain, the transmittingnode might simply erase the bits indicating a reservation or the like.

To synchronize the writing of bits or data into a slot, clocking must beprovided by either extracting it from the data transmitted on eachchannel assuming that these data are scrambled or block coded, or by acommon clocking channel. The common clocking channel is controlled byone (master) node having means for generating a clock signal. Toincrease the redundancy of the transmission system, several of the nodesmight be equipped to control the clock channel. A common clock channelhas the advantage that no specific coding or scrambling of thetransmitted data is necessary and that, further, a node remainssynchronized even when tuning to another channel.

Using the common clock channel as reference, it is possible to provide anode with means for bit, byte, or slot synchronization.

With an accurate synchronization, the network can be furnished withso-called isochronous slots in case that real time connections require astrict repetition of free slots for certain nodes by effecting a node togenerate slots at fixed time intervals reserved for only one of thenodes transmitting data to its channel.

The invention is especially suitable for data transmission systemshaving an optical transmission medium divided into several channels bywavelength division multiplexing (WDM) as optical fibers are offering alarge bandwidth for transmission.

DESCRIPTION OF THE DRAWINGS

The invention is described in detail below with reference to thefollowing drawings:

FIG. 1A shows an optical ring with several nodes.

FIG. 1B illustrates schematically different channels as open loops ofthe ring of FIG. 1A using WDM.

FIG. 2 shows the headend section and the transmit section of a nodeaccording to the invention.

FIG. 3 shows means to determine a fairness threshold within a node.

FIG. 4 shows a clock extraction circuitry of a node.

FIG. 5 shows components of a node according to the invention when usingspace division multiplexing for creating different channels.

DETAILED DESCRIPTION OF THE INVENTION

A basic network structure is illustrated by FIGS. 1A and 1B. FIG. 1Ashows a data transmission system based on an optical ring realized by asingle optical fiber 1 with several nodes 2 labeled A . . . F. WhileFIG. 1A depicts a specific physical embodiment of the invention, FIG. 1Bdescribing the multi-channel structure of the ring explains the basicidea of the invention in a more abstract and general way. Thetransmission medium, i.e. the optical fiber 1 of the describedembodiment, is divided by wavelength division multiplexing (WDM) into anumber of channels 11-17, which are shown in FIG. 1B. Each node is theonly destination for data transmitted on its assigned channel. Thougheach channel is assigned exclusively to only one node, it is possiblethat one node controls more than one channel. In the described example,one of the nodes 2 labeled with A, the master node, drives two channels11, 12, one (11) of which is used to provide a common clock signal toall nodes of the ring and for network management purposes, as will beexplained below.

Simultaneously, the node is acting as headend of its channel. Thus, itgenerates free slots 18 and absorbs these slots again after a round-tripon the fiber 1, i.e. after they have passed the other nodes 2 of thetransmission system. The direction of the data flow is indicated byarrow 19. In case of an optical ring, the invention establishesall-optical open loops, each starting and ending at a node A . . . F, asthe headend is the only point at which a conversion of the optical datasignals into electronic signals is performed.

Each node comprises a headend section which controls the channelassigned to it and a transmit section for communicating data to theother channels. Both parts of a node are schematically described byreferring to FIG. 2. In case of a single-fiber ring, the completeoptical signal of a wavelength channel assigned to the node is coupledout and an electrically regenerated signal is coupled back by theheadend section 21 (enclosed by a dashed line). Between the two couplers211, 212, the respective wavelength is suppressed. As optical couplersare readily available to a skilled person and not concern of thisinvention, no specific type is described. During the operation of thetransmission system, the wavelength assigned to a node remains fixed. Byusing a tuneable coupler 211, it is possible to change the assignationduring an initializing or a reconfiguration procedure. A tuneablecoupler is for instance implemented by a a tuneable acousto-opticalfilter that is able to separate at least one selected wavelength channelfrom all WDM channels passing the node while suppressing the signals ofthe selected wavelength channel on the optical fiber 1, sufficiently.

In the preferred embodiment, the coupler is followed by means 213 forconverting an optical signal into an electrical one, e.g. a photo diodeor an array of photo diodes, and a receive buffer 214 storing thereceived data to prevent a loss of data in case that incoming data ratetemporarily exceeds the rate in which the data are absorbed by theconnected node.

As all slots are received by the headend, a slot generator 215 isprovided to generate new slots. The electrically generated slots areconverted into optical signals by an electro-optical converter 216. Toimplement tuneable electro-optical converter 216, a tuneable laser diodeor an array of laser diodes each having a different wavelength is used.The coupler 212 feeds the slots into the optical fiber 1. It isimportant to note that all data assigned to other channels orwavelengths pass the headend without conversion.

Before explaining in detail the control means 217, 218, 219 which havean impact on the slot generator 215 of the headend 21, the transmitsection 22 of the node will be described. The transmit section 22 of anode comprises a broadband coupler 221, a tunable wavelength filter 222to select the wavelength at which a transmission is projected, and anopto-electrical converter 223 connected to means 224 for detecting thestatus of a passing slot of said channel and for synchronizing the datatransmission to a free slot ensuring that the data are accuratelywritten in the passing slot at the appropriate location, i.e. in thepayload field of the slot. To store data in case that no free slots areimmediately available on the channel, the transmit section 22 isadditionally provided with a transmit buffer 225. Depending on thesignal received from control 224, either the queue length (QL) as storedin register 226 or the data stored in the transmit buffer 225 aretransmitted via the tuneable electro-optical converter 227, whichcomprises either a tuneable laser diode or an array of laser diodes withdifferent wavelengths. The optical signal is coupled into the ring 1 bya coupler 228. A delay line 20 within the optical fiber 1 between thereceiving coupler 211 and the transmitting coupler 212 of the headendsection 21 compensates for the electronic or optical processing delay inthe control path, thus allowing writing at the accurate position of theslot detected by the control means 224.

As mentioned above, it is an important aspect of the invention that theheadend part of each node exclusively controls the data flow on itschannel by generating slots to which all other nodes can contribute datasignals, i.e. payloads, having said node as destination.

Besides the slot generation, each headend preferably comprises furthermeans 217, 218, 219 to control the access to its channel. The fairnesscontrol 217 guarantees that all nodes tuned to the channel obtain anequal share of the channel throughput capability. The flow control 218regulates the data flow such that the receiver can always accept all thedata transmitted. And the congestion control 219 prevents data unitsfrom being lost due to a completely filled receive buffer. The describedexample of the invention achieves these controls by using four bits toindicate the status of a slot.

A busy bit indicates that the slot cannot be accessed by a node fortransmitting data. A reserve bit is used to mark a slot as reserved inconnection with the fairness control. And a guarantee bit is set toindicate a priority reservation. In addition, it can be used togetherwith the aforementioned reserve bit to identify a guaranteed bandwidthslot. A guaranteed bandwidth is required by real time applications, suchas interactive voice and video transmission or remote process control.The fourth bit, i.e. the release bit, indicates that the reservation dueto any of the three other bits is cancelled and, hence, the slot can beaccessed by any node. The release bit gains importance in the transientphase wherein the demand for slots decreases after a period of excessdemand; reserved or guaranteed slots which are not needed by thetransmitting nodes become available to the other nodes on the ring.Apparently, only the busy and reserve bits are necessary for fairness,flow, and congestion control. The other two bits are used advantageouslyfor specific and advanced purposes.

In the following, the fairness control will be described in detail. Itis the scope of the fairness control to reduce the impact of theposition of a node within the bus or ring topology. Without a fairnesscontrol the first node situated `downstream` of the headend node of theconsidered channel has free access to every slot generated by thechannel's headend effectively blocking the data transmission of allfollowing nodes for the period it is transmitting. To establish afairness control, the headend of the channel periodically issues aspecial slot, i.e. the reserve command. The periods are referred to asreservation cycles. Apart from short rings carrying less than aroundhundred slots simultaneously on the transmission medium, a reservationcycle is a few slot time units larger than the round-trip delay. Thereserve command collects from each node currently tuned to the channelthe amount of data, i.e. the queue length (QL), waiting for transmissionon that channel.

Further, the entries to the reserve command must not be identified byaddresses indicating the transmitting node. Only an additional flag isrequired to notify whether a node specifies its queue length for thefirst time or not. Before the headend issues the reserve command, itmarks all empty entries by a zero and all entries used in the previousreserve command by a one. A node making an entry for the first timedetects the first location in the reserve command marked by a zero andstores the position of said location. Further, the current value of QLis written at this location. The node continues to use the markedlocation in the reserve command until it ceases to transmit on thechannel.

If the sum of the required slots as reflected by incoming queue lengthsexceeds the transmission capacity during a reservation cycle, thefairness control 217 within the headend section 21 of a node determinesa fairness threshold value (TH). Means for determining a threshold valuewithin microseconds is described, for example, in the Europeanapplication No. 93810215.9, now EP-A 0617372 having the title `Apparatusfor Determining the Optimal Value of a Control Parameter and Use of theApparatus`. The method described in the aforementioned application isbased on treating the demand QL for each node as piecewise linearfunction using the number of slots as independent variable. Toaccelerate the determination of the threshold, the second derivatives ofthese functions are summed rather than the values QL, themselves. Due tothe simple structure of the functions, the second derivatives equal +1at the position zero (slots) and -1 at the position QL (slots) and zero,elsewhere.

To determine a threshold for the next reservation cycle, firstly, eachnode has means to determine the actual demand of a transmitting nodetaking into account that that node has transmitted data during thecurrent reservation cycle after writing his demand to the currentlyreceived reserve command. The amount of data already transmitted eitherequals the amount of data QL(old) reported by each node in the previouscycle or the previous threshold value TH; this amount is subtracted fromthe demand of each node gathered from the current reserve command.Secondly, these differences, as representing the actual demand of eachnode for the considered channel, are sequentially supplied via theaddress line 31 to a gate array GA and a random access memory RAM asshown in FIG. 3.

For adding the second derivatives only the gate array GA, the RAM, andthe incrementer/decrementer 33 of the whole circuit are active. Thevalue zero and the actual demanded number of slots as calculated areapplied via address lines 31 to the gate array GA and the random accessmemory RAM for each node, consecutively. In the described example, theinput of the second derivative is done by the help of theincrementer/decrementer 33, as the slope of each function only changesby an amount of 1. The contents of the memory location in the RAM at theaddress zero is incremented by 1, whereas the value of the other memorylocations at the addresses QL is decremented by 1 for request entries.During this summation process the gate array GA keeps track of alladdresses at which an entry has been made. After the input from allnodes has been stored, accordingly, the cycle length values just aboveand below the desired cycle length, together with the correspondingthreshold values are computed.

The gate array, when strobed, will consecutively output all theaddresses at which a value had been entered. By means of a subtractercircuit 34 the difference between consecutive addresses is obtained.

The output from the gate array is also used to address the RAM. The RAMwill output the sums of the second derivatives as stored at theaddressed memory locations. This sum corresponds to a difference in theslope of the sum S of the requested slots. The differences in slope areintegrated by means of an adder 36 and a register 37, resulting in thefirst derivative S* of S.

To perform the second integration these slope values S* are multipliedin the following circuit 38 with the value from the subtracter 34. Thisoperation results in the difference between two consecutive values atupper and lower end of a linear segment of the sum S. By summing allthese difference values with the help of another adder 39 and a register310 all values of the function S itself are consecutively obtained.

As soon as the calculated cycle length value exceeds the desired cyclelength reference value, stored in register 312, a load pulse stores thecycle length just above and just below the desired value in theregisters 316 and 315, together with the corresponding threshold values,which are stored in registers 314 and 313. At this point, one of the twothreshold values or a value derived by linear interpolation between thetwo values may be selected.

Since the multiplier is the slowest element in the chain, and sincemultipliers exhibit multiplication times of 50 ns or less, the thresholdcan easily be derived in less than 1 μs (assuming 16 active nodes).

The threshold value gives the maximum number of slots available to anode during the following reservation cycle. It is broadcast to thenodes together with the next reserve command. A corresponding number ofslots in the reservation cycle are marked by the headend as reserved bysetting the reserve bit to "1". If a threshold value other than zero isgiven, every transmitting node stores said value and writes its currentqueue length (QL) into the reserve command. A node is allowed to accessfree reserved slots up to either the threshold value or the QL valuewritten in the preceding reserve command, whatever is less. For thatpurpose, the QL value as specified in the reserve command is stored bythe node. The following components of the transmit section are used tohandle the reserve command. The QL value, written to the new reservecommand is stored in a first of two pipelined registers, while the oldQL value written to the previous reserve command is pushed into thesecond register. A comparator compares the old QL value to the new THvalue received from the new reserve command and controls a multiplexerwhich stores the minimum of either QL(old) or TH into a counter. Thiscounter keeps track of the number of slots transmitted by the nodewithin the current reservation cycle and terminates the transmissionwhen the stored value is decremented to zero.

Assuming for example four nodes active on the considered channel with ademand of QL=10, 5, 12, and 3, respectively, the reserve command gathersa total demand of 30 exceeding a predetermined reference value, e.g. 25.The headend determines a threshold value of 9 resulting in a cyclelength for the following reservation cycle of 26. The reserve commandissued next reports the threshold value 9 to the control means 224 whichregulate the data transmission of a node to the channel. The nodes,thus, occupy 9, 5, 9, and 3 slots of the next reservation cycle,respectively.

The reserve command which broadcast the TH of 9 to the nodessimultaneously collects a demand of QL=22, 7, 20, and 15 of the nodesfor the next cycle. The headend determines the actual demand of thenodes for the next cycle by subtracting the slots transmitted during thecurrent cycle.

The remaining demand becomes, therefore, 22-9, 7-5, 20-9, and 15--3, forthe four nodes, giving a sum of 38. Thus, the next cycle starts with athreshold of 8 and, in accordance with the remaining demand of thenodes, a cycle length of 26 slots. If a node does not make use of the(full) amount of reserved slots, because it was able to transmit to anon-reserved slot in the meantime, the control 214 transmits a "1" tothe release bit position of an unused slot, allowing other nodes totransmit data in these slots. The threshold determination is repeateduntil the capacity reference value is no longer exceeded by theaccumulated demand of the nodes. In this case, the TH is set to aspecial value, e.g. 0, indicating that the access limitation iscancelled for the following cycle. To prevent a frequent change betweenperiods of reserved and free access, it is proposed to define thecapacity reference to a value below the 100% capacity of the system.

In order to control the data flow, the headend 21 is able to mark acertain fraction of the generated slots as busy instead of free. Asshown in FIG. 2, the flow control means 218 monitor the content of thereceive buffer 214. When this content reaches a critical value, the slotgenerator 215 throttles the generation of free slots. This throttlingdoes not disturb the data transmission to other destinations, becausethese transmission occur in different channels. Instead from the buffer214, the flow control 218 may receive its input signal also from anothercircuitry when, for instance, the receiving node is an access point to acurrently congested network, e.g. a bridge or a router.

A congestion control 219 prevents a loss of data due to an overflow ofthe receive buffer 214 in the headend. The congestion control causes theslot generator 215 to issue an special slot, i.e. the congestioncommand. The detection of a congestion command by the other nodesprevents them from transmitting further data, until the congestioncommand is rendered into a go-ahead command by the headend. Thecongestion command is issued by the headend when a busy slot arrives andthe receive buffer is full. After the opto-electrical conversion 213,the busy slot and all following slot are no longer switched to thebuffer 214 but redirected to the slot generator 215, which fills thefreshly generated slots with the data of the received slot. Thus, theslots are relayed for another round-trip around the loop formed by theoptical fiber 1. All other slots follow, independently of the bufferhaving gained free capacity in the meantime, until the congestioncommand returns to the headend. When it returns and the receive bufferhas sufficiently been emptied, the command is converted into a go-aheadcommand, and the recycled busy slots are received, else they are forcedto pass the ring, again. The slots remain in their correct sequence.

For the synchronization of the data transmission, the system preferablyprovided with a common clock channel controlled by the master node. Incase of a WDM optical ring, a specific wavelength λ₀ is designated asclocking channel for all nodes. The common clock channel provides a bit,word, and slot synchronization, as shown in FIG. 4, as well as a timingframe, e.g. of 125 μs, for real-time applications. In addition, it canbe used as service channel for network management. A coded diphasecoding scheme can, for instance, be used to ease the clock extraction.From the clock channel 11 carrying the coded diphase clock signal, apart of said signal is coupled out via the coupler 42 and transducedinto an electrical signal by the opto-electrical converter 43. By usinga phase-locked loop 44, the bit clock is detected. A serial-to-parallelconverter 45 converts the bit stream into an eight-bit wide format,while a CRC (Cyclic Redundancy Check) checker 46 keeps track of the slotboundaries. The CRC checker is also used to periodically reset a counter47. If it is not reset, it produces a carry output which causes theserial-to-parallel converter 45 to skip a bit position. This process isrepeated until the byte boundary is found.

Thus, a a bit clock, a word clock, and a slot boundary clock signal canbe extracted and exploited for the transmission of the data to the ring.The common clock channel simplifies the receiver and transmitter of thenodes as no scrambler/discrambler or encoding/decoding hardware isrequired. Further, all transmitting channels are identicallysynchronized and, thus, every transmitter can tune to another channelwithout a resychronization. Only a phase correction is needed, whenchanging the wavelength, since signals of different wavelengthspropagate with different speeds.

The master node and the clock channel are used to allocate thewavelength channels to the nodes of the system, i.e. to tune the headendof a node to a certain wavelength at network initialization time or whena network reconfiguration is executed. Other network management taskscan be additionally performed by the master node. For example, it ispossible to change the wavelength assigned to a node in areconfiguration of the whole transmission system by sending controlsignals to the tuneable devices in the headend section of each node.

A particular write pattern is applied to the four status bits, i.e. thebusy, release, reserve, and guarantee bit, ensuring that bits are erased(or nullified) only at the headend section. The headend generates in thedescribed example five different types of slots: If none of the statusbits is set (to "1"), the slot is a free slot. A "1" at the reserve bitposition is used to indicate a free reserved slot, while an additional"1" at the guarantee bit position assigns a free guaranteed slot. If a"1" is set only at the guarantee bit position, a free priority slot isindicated. An isochronous channel slot can be defined by having a "1" atthe busy and guarantee bit position. Whereas these bits are set by theheadend which generates the slots, the transmitting node mark a usedslot as busy by setting the busy bit. Further, a node can indicate thatunused reserved, guaranteed, or priority slots are made free for beingused by any node by setting the release bit to "1". These free releasedslots are marked busy by setting the busy bit. In the described scheme,bits are only set but not deleted (except at the receiving node)providing an advantage in optical signal processing where erasing alight signal on a particular wavelength channel from the transmissionmedium is more difficult to achieve than adding a light signal.

FIG. 5 shows the another example of the invention wherein the multiplechannels are realized by cables with parallel optical fibers 51. In thisexample, the headend section comprises an optical switch 56 operatedeither manually or electronically in case that the network isreconfigured. In the transmit section, the tunable filters andtransmitting lasers are replaced by detector and laser arrays 52, 53controlled by electronic multiplexing means 54, 55. By implementingthese changes, the medium access control scheme of the invention remainsbasically unchanged.

What is claimed is:
 1. A digital data transmission system comprising:aplurality of nodes; a transmission medium dividable into a plurality ofchannels connecting said nodes, with each of said nodes assigned to atleast one of said channels for receiving data from the other nodes, eachnode further comprising:a coupling means to transmit data on channelsassigned to other nodes; a slot generating means for generating slots onthe channel assigned to the node for receiving data which has beenasynchronously inserted into the assigned channel by the other nodes,said slot generating means able to mark generated slots as reserved; afairness control means for controlling said slot generator means toprovide balanced access to said slots on said assigned channel for theother nodes, said fairness control means determining the amount of datato be transmitted to the node and causing said slot generator means tomark one or more generated slots as reserved; and, a transmissioncontrol means for detecting a reserved slot on any one of the pluralityof channels and for controlling said coupling means to prevent insertionof data to a reserved slot.
 2. The digital data transmission system inaccordance with claim 1, wherein the fairness control means comprises:afirst means for controlling the slot generating means as to periodicallygenerate a reserve command which broadcasts the threshold value (TH) forits assigned channel to the other nodes and gathers a value (QL)indicating the amount of data waiting to be transmitted on its assignedchannel from each of the other nodes; a second means for determining athreshold value (TH) for the next reserve command, and, wherein thetransmission control means comprises means for determining the amount ofdata to be transmitted to another node according to said threshold value(TH) sent by said other node in said reserve command associated with theassigned channel for said other node.
 3. The digital data transmissionsystem in accordance with claim 1, having at least one node furthercomprising:a buffer means for storing the data received from thetransmission medium; and, a flow control means for controlling the slotgenerating means in accordance with the extent to which said buffermeans is occupied.
 4. The digital data transmission system in accordancewith claim 1, having at least one node further comprising:a buffer meansfor storing the received data; and, a congestion control means forcontrolling the slot generating means in accordance with the extent towhich said buffer means is occupied and using the assigned channel asintermediate storage when said buffer means is full.
 5. The digital datatransmission system in accordance with claim 1, having at least one nodefurther comprising:a buffer means for storing the received data; and acongestion control means for controlling the slot generating means inaccordance with the extent to which said buffer means is occupied andusing the channel as intermediate storage, wherein said congestioncontrol means comprises means for controlling the slot generating meansto generate a congestion command for causing all other nodes to stopinsertion of data on its assigned channel and means for relaying datareceived from its assigned channel back to the transmission medium. 6.The digital data transmission system in accordance with 1, having atleast one node further comprising:a priority access control means orguaranteed bandwidth control means for controlling the slot generatingmeans to periodically generate a poll slot collecting the demand forpriority or guaranteed bandwidth slots on its assigned channel from eachof the other nodes and to generate slots marked with a priority orguaranteed status, depending on the number of demanded priority orguaranteed slots and the capacity of its assigned channel.
 7. Thedigital data transmission system in accordance with claim 1, having atleast one node wherein the transmission control means further comprisesmeans for marking a reserved slot as released.
 8. The digital datatransmission system in accordance with claim 1, having master nodefurther comprising:a means for generating a clock signal on a commonclock channel.
 9. The digital data transmission system in accordancewith claim 8, each node further comprising:a means for bitsynchronization, byte synchronization, or slot synchronization, usingthe clock signal from the common clock channel as reference.
 10. Thedigital data transmission system in accordance with claim 1, 2, 3, 4, 5,6, 7, 8, or 9 wherein the transmission medium is an optical transmissionmedium divided into the plurality of channels by wavelength multiplexingdivision (WDM).
 11. A node adapted for use in a digital datatransmission system having a plurality of nodes and a transmissionmedium dividable into a plurality of channels connecting said nodes,with each of said nodes exclusively assigned to at least one of saidchannels as a data receiving node, said node comprising:a coupling meansto transmit data on a plurality channels; a slot generating means ableto generate slots on a first channel exclusively assigned to the nodefor receiving data which has been asynchronously inserted into the firstchannel, said slot generating means able to mark generated slots asreserved; a fairness control means for controlling said slot generatormeans to provide balanced access to said slots on said first channel bydetermining the amount of data to be transmitted to the node and causingsaid slot generator means to mark one or more generated slots asreserved; and, a transmission control means for detecting a reservedslot on any one of the plurality of channels and for controlling saidcoupling means to prevent insertion of data to a reserved slot.
 12. Thenode in accordance with claim 11 wherein the fairness control meansfurther comprises:a first means for controlling the slot generatingmeans to periodically generate a reserve command in a poll slot whichbroadcasts a threshold value (TH) for the assigned channel and gathers avalue (QL) indicating the amount of data waiting to be transmitted tothe node on the assigned channel; a second means for determining athreshold value (TH) for the next reserve command, and, wherein thetransmission control means comprises means for determining the amount ofdata to be transmitted from the node according to a received thresholdvalue received by the node in a reserve command from a poll slot inanother channel.
 13. The node in accordance with claim 11, comprising:abuffer means for storing the data received from the transmission medium;and, a flow control means for controlling the slot generating means inaccordance with the extent to which said buffer means is occupied. 14.The node in accordance with claim 11, comprising:a buffer means forstoring the received data; and, a congestion control means forcontrolling the slot generating means in accordance with the extent towhich said buffer means is occupied and using the assigned channel asintermediate storage when said buffer means is full.
 15. The node inaccordance with claim 11, comprising:a buffer means for storing thereceived data; and a congestion control means for controlling the slotgenerating means in accordance with the extent to which said buffermeans is occupied and using the channel as intermediate storage, whereinsaid congestion control means comprises means for controlling the slotgenerating means to generate a congestion command for halting theinsertion of data on the assigned channel and means for relaying datareceived from the assigned channel back to the assigned channel.
 16. Thenode in accordance with 11 comprising:a priority access control means orguaranteed bandwidth control means for controlling the slot generatingmeans to periodically generate a poll slot for collecting the demand forpriority or guaranteed bandwidth slots for the assigned channel and togenerate slots marked with a priority or guaranteed status, depending onthe demand for priority or guaranteed slots and the capacity of theassigned channel.
 17. The node in accordance with claim 11 wherein thetransmission control means comprises means for marking a reserved slotas released.
 18. The node in accordance with claim 11 furthercomprising:a means for generating a clock signal on a clock channel. 19.The node in accordance with claim 11, further comprising:a means for bitsynchronization, byte synchronization, or slot synchronization, using aclock signal from a clock channel as reference.